1. Field of the Invention
This invention relates generally to the fabrication of semiconductor devices and, more particularly, to methods for curing spin-on dielectric materials used in semiconductor devices.
2. Description of the Prior Art
Interlayer dielectrics utilized in multilevel interconnection in manufacturing of ultra-large scale integrated circuits have requirements to provide gap filing into high aspect ratio gaps (between metal conductors) and a high flatness of the topology (planarization). To meet these requirements, numerous interlevel dielectric formation processes have been investigated. Tetraethylorthosilicate (TEOS) based chemical vapor deposition (CVD), biased high density plasma CVD combined with chemical mechanical polishing (CMP) have been developed. There are a number of problems with these technologies including: particle generation, process reliability, cost and gap filling capability. Spin-on-glass processes have been utilized and offer simplicity, better gap filling and planarization than these other techniques.
In integrated circuit process technology, the fabrication of reliable interconnect structures with high yields require the deposition of metallization layers of uniform thickness and their subsequent patterning while preserving critical dimensions and line widths. These process goals are difficult to realize unless the substrate is planarized prior to the metallization step. That is, the interlayer dielectric must fill the space between the closely packed vertical wall metal lines of the lower interconnect level so as to produce a smooth topography. Spin-on-glass materials are limited in terms of thickness by their tendency to crack when made in thick layers and cured. Spin-on-glass liquids typically consist of a silicon oxygen network of polymers, one of which is siloxane, dissolved in an organic solvent (typically a combination of a high boiling point solvent and a low boiling point solvent). The dissolved spin-on-glass material is coated onto the semiconductor wafer by spinning at high speed. The spin-on-glass material fills gaps and the uneven topography of the integrated circuit wafer, thereby planarizing it. After spinning onto a substrate, low boiling point solvents are expelled via a low temperature hot plate bake. The wafer is then heated in vacuum or nitrogen to 300xc2x0-400xc2x0 C. This removes higher boiling point solvents and components which can cause cracking and corrosion at subsequent process steps. Very thin coatings are applied this way. If thick coatings are used, the spin-on-glass film cracks due to shrinkage in the baking steps. If a thicker coating is required, multiple coatings must be applied and vacuum baked. This is undesirable because of the time consuming process steps involved and the built up film can still crack in the final cure. The final step in the forming of the spin-on-glass layer is curing at very high temperature. While temperatures as high as 800xc2x0 to 900xc2x0 C. may be required to obtain preferable film properties, in integrated circuit fabrication, the maximum temperature at which spin-on-glass film can be cured is often limited to about 450xc2x0 C. because of the possibility of melting aluminum interconnects or adversely impacting other parts of the integrated circuit.
After a cure at this lower temperature, some spin-on-glass materials contain significant amounts of residual silanols and carbon, and can readily absorb water. The dielectric properties (for example, dielectric constant) of a spin-on-glass film are influenced by the silanol and water content of the film. In the fabrication of integrated circuits it is important to have a low dielectric constant in the spin-on-glass since it becomes the insulating barrier between signal conductors and thus, will determine the upper operating frequency of a circuit. A major disadvantage of thermal methods of curing spin on glass at high temperature is cracking of the spin-on-glass film. Because the spin-on-glass is constrained in a horizontal plane (at the substrate interface), it can only shrink in the vertical direction. This creates great stresses in the spin-on-glass film when it has been baked at very high temperature. These stresses, and the subsequent cracking, have limited spin-on-glass applications despite their favorable attributes: planarization and good gap filling ability. Additionally, the etch rate of thermally cured spin-on-glass is poor compared to the etch rate of thermally grown oxide. It is, therefore, desirable to have some means of curing spin-on-glass at low temperatures to reduce the subsequent cracking of the spin-on-glass while improving its physical properties.
As the importance of low dielectric constant insulating materials has increased as characteristic dimensions of integrated circuits have decreased, organic polymer spin-on dielectric materials have been introduced. These materials also require a curing step at high temperature.
A number of different techniques have been proposed for curing dielectric materials. In U.S. Pat. Nos. 5,192,164 and 5,192,715, Sliwa proposed a technique where an etch back of the spin-on-glass creates unfilled voids between the metal interconnects allowing the spin-on-glass to expand and contract during hard curing without cracking. The drawbacks to this approach are extra process steps and potential of contaminants filing the unfilled voids. Subsequent high temperature baking can trap gases within the voids which can then subsequently cause corrosion of the metal conductors.
An alternative method of curing spin-on-glass is by ion implantation. In U.S. Pat. No. 5,192,697, Leong devised a method of curing spin-on-glass using ion implantation, which allows curing at lower temperatures while improving the oxide etch rate. The high energy ions impinge on the spin-on-glass layer causing, heating and crosslinking. Disadvantages of this technique are that only relatively thin layers can be cured (xcx9c1000-2000xc3x85), it requires high vacuum environments ( less than 2xc3x9710xe2x88x925 Torr) and expensive equipment. Also, high energy ions can cause damage to the lattice structure of the oxides and radiation damage to the underlying active circuits. Even higher and more damaging implant energies are required to penetrate thicker oxide layers. As shown by Moriya (N. Moriya et al., xe2x80x9cModification Effects in Ion-Implanted SiO2 Spin-in-Glass,xe2x80x9d J. Electrochem. Soc., Vol 140. No. 5, May 1993. pp. 1442-1450), damage induced by the high energy ions can drastically modify the spin-on-glass (SOG) film properties.
Another technique that has been proposed to cure spin-on-glass is utilizing ultra-violet radiation and a hotplate. In U.S. Pat. No. 4,983,546, Hyun et. al. claim to achieve spin-on-glass properties that are better than thermally cured spin-on-glass cured at 420xc2x0 C. However. the disclosed process does not produce the superior qualities of the spin-on-glasses that have been cured at 800xc2x0-900xc2x0 C. There are still carbon and silanols present that can cause subsequent cracking and delamination due to water absorption.
Young-Bum Koh el. al. (xe2x80x9cDirect Patterning of Spin-on-Glass by Focused Ion Beam Irradiation,xe2x80x9d Jpn. J. Appl. Phys., Vol 31, (1992) pp. 4479-4482) utilized focused ion beam irradiation to crosslink the spin-on-glass. They compare ion beam irradiation of the spin-on-glass with thermal treatments. Whereas carbon is eliminated in thermal cures of 850xc2x0 C., high doses of ion beam irradiation show a reduction in the carbon but not elimination. They also report that electron beam irradiation requires 2-3 orders of magnitude higher dose than ion beam irradiation to crosslink the SOG material. This would indicate that electron beam processing of SOG would require long process times.
Crosslinking of siloxane type materials by electron beam irradiation have been reported by numerous workers for direct patterning and use in lithography. Electron beams have been considered for crosslinking of spin-on-glass films. A. Imai and H. Fukuda (xe2x80x9cNovel Process for Direct Delineation of Spin on Glass (SOG),xe2x80x9d Japanese J. Appl. Physics, Vol. 29, No. 11, 1990, pp. 2653-2656) show a method of crosslinking spin-on-glass using a freely focused electron beam to make the SOG insoluble in a solvent and thereby patterning it directly on a semiconductor substrate. However, Imai and Fuimda only teach the use of an electron beam for patterning the spin-on-glass, not for final curing.
Using high energy electrons to performn final curing of SOG materials is not obvious due to the history of induced damage to semiconductor oxide layers by relatively low dosage exposures of high energy electrons by electron beam lithography tools. Therefore, exposing semiconductor oxides to orders of magnitude higher doses of electrons would seem an anathema to high yield device processing. Moreover, there have been a myriad of deleterious effects found when electron beams expose semiconductor oxides including: charge buildup, production of electronic states at the Si-SiO2 interface, and induced electron traps in oxides. These effects cause the following problems in MOS devices: threshold voltage shifts, channel mobility degradation in transistors, and hot electron effects. Doses utilized in electron beam lithography are in the range of 5 to 100 xcexcC/cm2 . It would seem that the orders of magnitude higher doses that might be required to fully cure spin-on-glass would cause massive damage to active oxides in semiconductor devices. This may have heretofore discouraged attempts to utilize electron beams for SOG curing.
There is a wealth of prior art showing electron beam damage to semiconductor oxides when irradiated with high doses of electron beam making electron beam irradiation an unobvious choice for curing SOG materials. When high energy electrons are incident on an oxide layer, they generate electron hole pairs. Once generated the pairs can be separated due to a field in the oxide. The electron, being very mobile, transports relatively rapidly to the surface or a conductor layer, whereas the hole may be trapped near the silicon dioxide/silicon interface. This trapping process is referred to as a positive charge build up. Positive charge build up is dependent on temperature. The lower the temperature, the higher the charge build up as the holes are less mobile at lower temperatures. Electronic states at the silicon dioxide/silicon interface cause a subsequent CV curve to be stretched out along the voltage axis instead of an ideal parallel shift. Stretch-out occurs because less silicon bandbending is achieved at a given gate bias when interface states are present.
Interface states can be negatively charged and can affect the threshold voltage in MOS transistors. Electron beam irradiation can cause the creation of neutral electron traps in silicon dioxide films.
Radiation induced neutral electron traps can enhance hot electron instabilities. For MOS transistors with small dimensions, hot electron emission from the silicon substrate into the silicon dioxide layer can occur. A portion of these electrons maybe trapped. This trapped charge causes undesirable effects such as threshold voltage shifts and transconductance degradation.
While drawbacks of electron beam curing of some materials used in semiconductor fabrication have been reported in the prior art, there remains a need for a method for curing spin-on dielectric insulators that avoids the problems of thermal curing. It would be desirable to develop a method of curing that provides comparable or improved properties of dielectric films, as compared with thermally cured films, at lower temperatures and shorter process times.
The invention disclosed utilizes a large area electron beam to irradiate spin-on-glass or spin-on-polymer dielectric insulating materials in a soft vacuum environment in combination with infra-red lamps to indirectly heat the materials. Electron beam irradiation of spin-on dielectric materials provides dielectric films with similar or improved properties compared with the properties of the same materials that have been thermally cured. For specified electron beam total dose, temperature of the material, and ambient atmosphere, electron beam curing can provide cured material with lower dielectric constants than thermal curing. In addition, electron beam curing results in decreasing the etch rate in a buffered oxide etch solution and in modifying the rate of chemical mechanical polishing of the material as compared with thermal curing. Further, process times for electron beam curing are shorter than process times of typical thermal cure processes.
According to an aspect of the present invention, a method of modifying the properties of a layer of spin-on-glass or spin-on-polymer includes irradiating the layer with a large-area electron beam in a non-oxidizing environment while simultaneously applying heat to the layer until a sufficient electron dose has accumulated to provide a layer with a dielectric constant less than or about equal to the dielectric constant of a thermally cured layer of the same material. A total dose of between 10 and 100,000 microCoulombs per square centimeter (xcexcC/cm2) may be used. Preferably, a dose of between 100 and 10,000 xcexcC/cm2 is used, and most preferably a dose of between about 2,000 and 5,000 xcexcC/cm2 is used. The electron beam is delivered at an energy of between 0.1 and 100 keV, preferably at an energy between 0.5 and 20 keV, and most preferably at an energy between 1 and 10 keV. The electron beam current ranges between 0.1 and 100 mA, more preferably between 1 and 30 mA and most preferably between about 3 and about 20 mA. The entire electron dose may be delivered at a single voltage. Alternatively, the dose is divided into steps of decreasing voltage, which provides a uniform dose process in which the material is cured from the bottom up. During the electron beam curing process, the wafer is kept at a temperature between 10xc2x0 and 1000xc2x0 C. Preferably, the wafer temperature is between 30xc2x0 and 500xc2x0 C. and most preferably between 200xc2x0 and 400xc2x0 C.
According to another aspect of the present invention, a method of fabricating an integrated circuit device is provided. The method includes patterning a metal film on a substrate, depositing a layer of a spin-on glass or spin-on-polymer material on the metal film, irradiating the layer as described above, patterning a via into the irradiating layer, and filling the via with metal. The process may be repeated to produce multiple metal interconnect layers.